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| no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics c orporation . the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with an nec electron ics sales representative for availability and additional information. mos integrated circuit ? pd 720 200 usb 3 .0 host controll er document no. isg - yd1 - 000 127 - 0 5 date published april , 200 9 cp (n) preliminary data sheet 20 0 9 the ? pd720 200 is the universal serial bus 3.0 host controller , which complies with universal serial bus 3.0 specification, and intel s extensible host controller interface (xhci). the ? pd7 20 200 has pci express ? bus interface, and it is applicable for pci express solution for host pc system. the ? pd720 200 works up to 5 gbps for data transfer when connecting to usb 3.0 compliant peripherals, while maintaining compatibility with existing usb p eripheral devices. detailed function descriptions are provided in the following users manual. be sure to read the manual before designing. ? users manual : tbd features ? compliant with u niversal s erial b us 3.0 specification revision 1.0, whic h is released by usb implementers forum, inc - supports the following speed data rate as follows; low - speed (1.5 mbps) / full - speed (12 mbps) / high - speed (480 mbps) / super - speed (5 gbps) - supports 2 downstream ports for all speeds - s upports all usb compliant data transfer type as follows; c ontrol / bulk / interrupt / isochronous transfer ? compliant with intel s extensible host controller interface (xhci) specification revision 0.95 ? support usb legacy function ? c ompliant with pci express ? base specification 2.0 ? supports expresscard tm standard release1.0 ? supports pci express ? card electromechanical specification revision 2.0 ? supports pci b us p ower m anagement i nterface s pecification r evision 1. 2 ? operational register s are direct - mapped to pci memory space ? supports serial peripheral interface (spi) type rom ? system clock: 24 mhz crystal or 48mhz external clock. ? 3.3 v and 1. 0 5 v power supply ordering information part number package remark ? ? www.datasheet.co.kr datasheet pdf - http://www..net/
preliminary data sheet 2 ? pd 720 200 block diagram pci express gen2 interface : complies with pci express gen2 interface, with 1 lane. this block includes link and phy layer. xhci co ntroller : handles all supped required for usb 3.0, super - /high - /full - /low - speed. this block includes register interface from system. super - speed controller i/f : handles super - speed operation in xhci control block. high - speed c o ntroller i/f : handles hi gh - speed operation in xhci control block. full/low - speed controller i/f : handles full - /low - speed operation in xhci control block. usb3.0 ss link : is link layer defined in usb 3.0 specification, which maintains link connectivity with usb devices. usb3. 0 ss root hub : is a hub function in host controller for usb 3 .0 port managing. usb3.0 phy : for super - speed tx/rx usb2.0 sie : is serial interface engine, which controls usb 2.0 protocol sequence. usb 2.0 root hub : is a hub function in host controller for usb 2.0 port managing . usb2.0 phy : for high - /full - /low - speed tx/rx power sw i/f : is connected to external power switch for port power control and over current detection. spi interface : is connected to external serial rom. pll : internal pll. osc : internal oscillator block. p c i e x p r e s s g e n 2 i n t e r f a c e ( x 1 ) x h c i c o n t r o l l e r s u p e r - s p e e d c o n t r o l l e r i n t e r f a c e f u l l / l o w - s p e e d c o n t r o l l e r i n t e r f a c e h i g h - s p e e d c o n t r o l l e r i n t e r f a c e u s b 3 . 0 s s l i n k u s b 3 . 0 s s r o o t h u b u s b 2 . 0 s i e u s b 2 . 0 r o o t h u b u s b 3 . 0 ( s u p e r - s p e e d ) p h y u s b 2 . 0 ( h s / f s / l s ) p h y o s c / p l l s p i i n t e r f a c e p o w e r s w i / f e x t e r n a l s e r i a l r o m 2 4 m h z x t a l 4 8 m h z c l o c k i n p u t p c i e x p r e s s p o r t u s b p o r t 1 ( s s ) u s b p o r t 2 ( s s ) u s b p o r t 1 ( h s / f s / l s ) u s b p o r t 2 ( h s / f s / l s ) 3 . 3 v 1 . 0 5 v p o r t p o w e r c o n t r o l www.datasheet.co.kr datasheet pdf - http://www..net/ preliminary data sheet 3 ? pd 720 200 pin configuration ? 176 - pin plastic fbga ( 1 0 ? ? pd 720 200 f1 - dak - a bottom view gnd gnd u3 rx d n1 gnd u3 tx d n1 gnd u3 rx d n2 gnd u3 tx d n2 gnd gnd gnd gnd gnd a gnd gnd u3 rx d p1 gnd u3 tx d p1 gnd u3 rx d p2 gnd u3 tx d p2 gnd gnd gnd p e clkp p e clkn b gnd gnd gnd gnd gnd v dd 1 0 vdd10 vdd10 vdd10 vdd10 vdd10 gnd gn d gnd c gnd gnd gnd gnd v dd3 3 vdd10 vdd10 u3a vdd 33 u3a vss vdd10 gnd gnd p e txp p e txn d gnd gnd vdd10 vdd10 vdd10 vdd10 gnd gnd e vdd33 vdd33 gnd gnd gnd gnd gnd gnd gnd vdd33 p e rxp p e rxn f oci2b gnd gnd gnd gnd gnd gnd gnd vdd33 vdd33 gnd gnd g ppon2 oci1b gnd vdd10 gnd gnd gnd gnd vdd10 vdd10 perstb smib h ppon1 gnd gnd gnd gnd gnd gnd gnd gnd gnd auxdet psel j gnd gnd vdd10 vdd10 gnd gnd pe creqb pe wakeb k vdd33 vdd33 gnd gnd vdd33 vdd33 vdd10 gnd gnd vdd10 gnd gnd gnd gnd l xt2 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd spisck spiso m xt1 gnd u2a vss u2 pvss u2 dm 1 gnd u2 dm2 gnd vdd33 vdd33 vdd33 gnd spicsb spisi n gnd u2 avdd 33 rref gnd u2 dp1 gnd u2 dp2 gnd csel ponrstb gnd vdd33 gnd gnd p 14 13 12 11 10 9 8 7 6 5 4 3 2 1 www.datasheet.co.kr datasheet pdf - http://www..net/ preliminary data sheet 4 ? pd 720 200 1. pin functions this section describes each pin functions. power supply pin name ball no. buffer type function v dd 33 d10, f3, f13, f14, g3, g4, l9, l10, l13, l14, n4, n5, n6, p3 power +3.3 v power supply v dd1 0 c4, c5, c6, c7, c8, c9, d5, d8, d9, e3, e4, e11, e12, h3, h4, h11, k11, k12, l5, l8 power +1. 0 5 v power supply. u3 av dd33 d7 power +3.3 v power supply for analog circuit. u2 av dd 33 p13 power + 3.3 v power supply for analog circuit. v ss a1, a2, a3, a4, a5, a7, a9, a11, a13, a14, b3, b4, b5, b7, b9, b11, b13, b14, c1, c2, c3, c10, c11, c12, c13, c14, d3, d4, d11, d12, d13, d14, e1, e2, e13, e14, f4, f6, f7, f8, f9, f11, f12, g1, g2, g6, g7, g8, g9, g11, g12, g13, h6, h7, h8, h9, h12, j3, j4, j6, j7, j8, j9, j11, j12, j13 , k3, k4, k13, k14, l1, l2, l3, l4, l6, l7, l11, l12, m3, m4, m5, m6, m7, m8, m9, m10, m11, m12, m13, n3, n7, n9, n13, p1, p2, p4, p7, p9, p11, p14 power ground . u3 av ss d6 power ground for usb3.0 analog circuit . u2 av ss n12 power ground for usb2.0 analog circuit u2p v ss n11 power ground for internal pll. the mark shows major revised points. analog signal pin name ball no. direction buffer type active level function rref p12 analog reference resistor connection. www.datasheet.co.kr datasheet pdf - http://www..net/ preliminary data sheet 5 ? pd 720 200 system clock pin name ball no. direction buffer type active level function xt1 n 1 4 i osc oscillator in d u ring 24 mhz crystal mode, c onnect to 24 mhz crystal. in using external 48 mhz clock, this pin must be clamped to low. xt2 m 14 i/ o osc oscillator out or external clock input d u ring 24 mhz crystal mode, c onnect to 24 mhz crystal. in using external 48 mhz clock, this pin is used for external 48 mhz clock input signal. . csel p6 i 3.3v input clock select signal 0: 24 mhz crystal mode 1: 48 mhz external clock input system interface signal pin name ball no. direction buffer type active level function pon rst b p5 i 3.3v schmitt input low power on reset signal. when supporting wakeup from d3cold, this signal should be pulled high with system auxiliary power supply. smib h1 o 3.3v output (6ma) low system management interrupt signal smi# . www.datasheet.co.kr datasheet pdf - http://www..net/ preliminary data sheet 6 ? pd 720 200 pci express interface pin name ball no. direction buffer type active level function peclkp b2 i pcie pci express / usb3.0 100 mhz reference clock. peclkn b1 i pcie pci express / usb3.0 100 mhz reference clock. petxp d2 o pcie pci expre ss transmit data. petxn d 1 o pcie pci express transmit data. perxp f2 i pcie pci express receive data. perxn f1 i pcie pci express receive data. perstb h2 i 3.3v schmitt input low pci express perst# signal . pewakeb k1 o o pen d rain (6ma) low pc i express wake# signal . this signal is used for remote wakeup mechanism, and requests the recovery of power and reference clock input. pecreqb k2 o open drain (6ma) low pci express clkreq# signal . this signal is used to request run/stop of reference c lock for expresscard or mini c ard. auxdet j2 i 3.3v input high auxiliary power detect signal. this signal should be co nnected to auxiliary power line, when system support s remote wakeup from d3cold. psel j1 i 3.3v input pci express/express c ard select signal. : others : express c ard or mini card usb interface pin name ball no. direction buffer type active level function u3 tx d p (2:1) b 6 , b 10 o usb3 usb3.0 transmit data d+ signal for super - speed u3 tx d n (2:1) a 6 , a 10 o usb3 usb3.0 t ransmit data d - signal for super - speed u3 rx d p (2:1) b 8 , b 12 i usb3 usb3.0 receive data d+ signal for super - speed u3 rx d n (2:1) a 8 , a 12 i usb3 usb3.0 receive data d - signal for super - speed u2 dp (2:1) p8 , p10 i/o usb 2 usb 2.0 d ? signal for hig h - /full - /low - speed u2 dm (2:1) n8 , n10 i/o usb 2 usb 2.0 d ? signal for high - /full - /low - speed oci1 b oci2 b h13 g14 i 3.3v input low over - current status input signal for each downstream facing port . 0: over - current condition is detected 1: no over - c urrent condition is detected. ppon (2:1) h 14, j 14 o 3.3v output (6ma) high usb port power supply control signal for each downstream facing ports. 0: power supply off 1: power supply on www.datasheet.co.kr datasheet pdf - http://www..net/ preliminary data sheet 7 ? pd 720 200 spi interface pin name ball no. direction buffer type active le vel function spisck m2 o 3.3v output (6ma) spi serial flash rom clock signal. spicsb n2 o 3.3v output (6ma) spi serial flash rom chip select signal. spisi n1 o 3.3v output (6ma) spi serial flash rom data write signal. spiso m1 i 3.3v input spi serial flash rom data read signal. www.datasheet.co.kr datasheet pdf - http://www..net/ preliminary data sheet 8 ? pd 720 200 2. electrical specifications buffer list ? 3.3 v input buffer csel, auxdet, oci1b, oci2b, psel ? 3.3 v input s chmitt buffer ponrstb, perstb ? 3.3 v i ol = 6ma output buffer smib, ppon(2:1) ? 3.3 v i ol = 6ma bi - directional buffer spiso, spisi , spisck, spicsb ? n - ch open drain buffer pewakeb, pecreqb ? 3.3 v oscillator interface xt1, xt2 ? usb classic interface u2dp(2:1), u2dn(2:1) , rref ? pci express serdes peclkp , peclkn, petxp, petxn, perxp, perxn ? usb superspeed interface u3txdp(2:1), u3tx dn(2:1), u3rxdp(2:1), u3rxdn(2:1) www.datasheet.co.kr datasheet pdf - http://www..net/ preliminary data sheet 9 ? pd 720 200 terminology terms used in absolute maximum ratings parameter symbol meaning power supply voltage v dd 33 , v dd 10, u2 av dd 33, u3av dd33 indicates the voltage range within which damage or reduced reliability will not result when power is applied to a v dd pin. input voltage v i indicates voltage range within which damage or reduced reliability will not result when power is applied to an input pin. output voltage v o indicates voltage range within which damage or reduced reliab ility will not result when power is applied to an output pin. output current i o indicates absolute tolerance values for dc current to prevent damage or reduced reliability when current flows out of or into output pin. operating temperature t a indicates t he ambient temperature range for normal logic operations. storage temperature t stg indicates the element temperature range within which damage or reduced reliability will not result while no voltage or current is applied to the device. terms used in rec ommended operating range parameter symbol meaning power supply voltage v dd 33 , v dd 10, u2 av dd 33, u3av dd33 indicates the voltage range for normal logic operations occur when v ss = 0 v. high - level input voltage v ih indicates the voltage, which is applied to the input pins of the device, is the voltage indicates that the high level states for normal operation of the input buffer. * if a voltage that is equal to or greater than the min. value is applied, the input voltage is guaranteed as high level voltage. low - level input voltage v il indicates the voltage, which is applied to the input pins of the device, is the voltage indicates that the low level states for normal operation of the input buffer. * if a voltage that is equal to or lesser than the max. va lue is applied, the input voltage is guaranteed as low level voltage. term used in dc characteristics parameter symbol meaning off - state output leakage current i oz indicates the current that flows from the power supply pins when the rated power supply voltage is applied when a 3 - state output has high impedance. input leakage current i i indicates the current that flows when the input voltage is supplied to the input pin. www.datasheet.co.kr datasheet pdf - http://www..net/ preliminary data sheet 10 ? pd 720 200 electrical specifications absolute maximum ratings parameter symbol condition r ating unit s power supply voltage v dd 33 , u2 av dd 33 u3av dd33 ? 0.5 ~ ? 4.6 v v dd 1 0 ? 0.5 ~ ? 1. 4 v input voltage, 3.3 v buffer v i v i < v dd33 + 0.5v ? 0.5 ~ ? 4.6 v output voltage, 3.3 v buffer v o v o preliminary data sheet 12 ? pd 720 200 pci express int erface - p erstb and pewakeb signal timing s parameter symbol condition min. max. unit s power stable to p erstb inactive t pvperl figure 2 - 1 100 ms peclkp/peclkn stable before pe rstb inactive t perst - clk figure 2 - 1 100 ? s pci express interface C power - up and pecreqb signal timing s parameter symbol condition min. max. unit s power valid to pe creqb output active t pvcrl figure 2 - 9 100 ? s power valid to pe rstb input inactive t pvpgl figure 2 - 9 1 ms peclkp/peclkn stable before pe rstb inactive t pe_rstb - clk figure 2 - 9 100 ? s pci express interface C pecreqb clock control timing s parameter symbol condition min. max. unit s pec reqb d e - asserted high to clock parked t crhoff figure 2 - 10 0 ns pec reqb asserted low to clock active t crlon figure 2 - 10 400 ns www.datasheet.co.kr datasheet pdf - http://www..net/ preliminary data sheet 13 ? pd 720 200 pci express interface C differential transmitter (tx) specifications (refer t o pci express tm base specification revision 2. 0 for more information ) (1/ 2 ) parameter symbol 2.5gt/s 5.0gt/s . unit s unit interval ui 399.88(min) 4 00.1 2(max) 199.94(min) 200.06(max) ps differential peak to peak (p - p) tx v oltage swing v tx - diffp - p 0 .8(min) 1.2(max) 0.8(min) 1.2(max) v low power differential p - p tx voltage swing v tx - diffp - p - low 0.4(min) 1.2(max) 0.4(min) 1.2(max) v tx d e - emphasis level ration v tx - de - ratio - 3.5db 3.0(min) 4.0(max) 3.0(min) 4.0(max) db tx de - emphasis level ration v tx - de - ratio - 6db n ot specified 5.5(min) 6.5(max) db instantaneous lone pu lse width t min - pulse not specified 0.9(min) ui transmitter eye including all jitter sources t tx - eye 0.75(min) 0.75(min) ui maximum time between the jitter median and max deviation from the median t tx - eye - median - to - max - jitter 0.125(max) not specified ui tx deterministic jitter >1.5mhz t tx - hf - dj - dd not specified 0 .15(max) ui tx rms jitter > 1.5mhz t tx - l f - rms not specified 3.0 ps rms transmitter rise and fall time t tx - rise - fall 0.125(min) 0.15(max) ui tx rise/fall mismatch t rf - mismatch not specified 0.1(max) ui maximum tx pll bandwidth bw tx - pll 22(max) 16(max) mhz minimum tx pll bw for 3db peaking b wtx - pll - lo - 3db 1.5(min) 8(min) mhz minimum tx pll bw for 1db peaking b wtx - pll - lo - 1 db not specified 5(min) mhz tx pll peaki ng with 8mhz min bw p kgtx - pll1 not specified 3.0(max) db tx pll peaking with 5mhz min bw p kgtx - pll 2 not specified 1.0(max) db tx package plus si differential return loss rl tx - diff 10(min) 10(min) for 0.05 C 1.25ghz 8(min) for 1.25 C 2.5ghz db tx package plus si common mode return loss rl tx - cm 6(min) 6(min) db dc differential tx impedance z tx - diff - dc 80(min) 120(max) 120(max) ? ? tx ac common mode voltage (5gt/s) v tx - cm - ac - pp not specified 100(max) mvpp tx ac common mode voltage (2.5gt/s) v tx - cm - ac - p 20 not specifed mv transmitter short - circuit current limit i tx - short 90(max) 90(max) ma transmitter dc common - mode voltage v tx - dc - cm 0(min) 3.6(max) 0(min) 3.6(max) v absolute delta of dc common mode voltage during l0 and electrical idle v tx - cm - dc - active - idle - delta 0(min) 100(max) 0(min) 100(max) mv www.datasheet.co.kr datasheet pdf - http://www..net/ preliminary data sheet 14 ? pd 720 200 (2/ 2 ) parameter symbol 2.5gt/s 5.0gt/s . unit s absolute delta of dc common mode voltage between petxp and petxn v tx - cm - dc - line - delta 0(min) 25(max) 0(min) 25(max) mv electrical idle differential peak output voltage v tx - idle - diff - ac - p 0(min) 20(max) 0(min) 20(max) mv dc electrical idle differential output voltage v tx - idle - diff - dc not specified 0(min) 5(max) mv t he amount of voltage change allowed during receiver detection v tx - rcv - detect 600(max) 600(max) mv minimum time spent in electrical idle t tx - idle - min 20(min) 20(min) n s maximum time to transition to a valid electrical idle after sending an eios t tx - idle - set - to - idle 8(max) 8(max) ns maximum time to transition to valid diff signaling after leaving electrical idle t tx - idle - to - diff - data 8(max) 8(max) ns crosslink random timeout t c rosslink 1.0(max) 1.0(max) ns lane - to - lane output skew l tx - skew 500ps + 2ui(max) 500ps + 4ui(max) ps ac coupling capacitor c tx 75(min) 200(max) 75(min) 200(max) nf www.datasheet.co.kr datasheet pdf - http://www..net/ preliminary data sheet 15 ? pd 720 200 pci express interface C differential receiver ( r x) specifications (refer to pci express tm base specification revision 2.0 for more information) parameter symbol 2.5gt/s 5.0gt/s . unit s unit interval ui 399.88(min) 400.12(max) 199.94(min) 200.06(max) ps differential rx peak - peak voltage for common reference clock rx architecture v rx - diff - pp - cc 0.175(min) 1.2(max) 0.120(min) 1.2(max) v differential rx peak - peak voltage for data clocked rx architecture v rx - diff - pp - dc 0.175(min) 1.2(max) 0.100(min) 1.2(max) v receiver eye time opening t rx - eye 0.40(min) not specified ui max rx inherent timing error t rx - tj - cc not specified 0.40(max) ui max rx inherent timing error t rx - tj - dc not specified 0.34(max) ui max rx inherent deterministic timing error t rx - dj - dd - cc not specified 0.30(max) ui max rx inherent deterministic timing error t rx - dj - dd - dc not specified 0.24(max) ui m ax time delta between median and deviation from median t rx - eye - median - to - max - jitter 0.3(max) not specified ui minimum width pulse at rx t rx - min - pulse not specified 0.6(min) ui m in/max pulse voltage on consecutive ui t rx - ma x - min - ratio not specified 5(max) - m aximum rx pll bandwidth bw rx - pll - hi 22(max) 16(max) mhz minimum rx pll bw for 3db peaking bw rx - pll - lo - 3db 1.5(min) 8(min) mhz minimum rx pll bw for 1db peaking bw rx - pll - lo - 1db not specified 5(min) mhz rx pll peaking with 8 mhz min bw pkg rx - pll1 not specified 3.0 db rx pll peaking with 5mhz min bw pkg rx - pll2 not specified 1.0 db rx package plus si differential return loss rl rx - diff 10(min) 10(min) for 0.05 C 1.25ghz 8(min) for 1.25 C 2.5ghz db common mode rx return loss rl rx - cm 6(min) 6(min) db receiver dc single ended impedance z rx - dc 40(min) 60(max) 40(min) 60(max) ? ? dc differential impedance z rx - diff - dc 80(min) 120(max) not specified ? rx ac common mode voltage v rx - cm - ac - p 150(max) 150(max) mvp dc input cm input impedance for v>0 durin reset or power down z rx - high - imp - dc - pos 50k(min) 50k(min) ? dc input cm input impedance for v<0 during reset or power down z rx - high - imp - dc - neg 1.0k(min) 1.0k(min) ? electrical idle detect threshold v rx - idle - det - diffp - p 65(min) 175(max) 65(min) 175(max) mv unexpected electrical idle enter detect threshold integration time t rx - idle - det - diff - enter time 10(max) 10(max) ms lane to lane skew l rx - skew 20(max) 8(max) ns www.datasheet.co.kr datasheet pdf - http://www..net/ preliminary data sheet 16 ? pd 720 200 usb 3.0 superspeed interface C differential transmitter (tx) specifications (refer to universal serial bus 3.0 specification revision 1 .0 for more information) transmit ter normative electrical parameters parameter symbol min max unit s unit interval ui 199.94 200.06 p s differential p - p tx voltage swing v tx - diff - pp 0.8 1.2 v low - power differential p - p tx voltage swing v tx - diff - pp - low 0.4 1.2 v tx de - emphasis v t x - de - ratio 3.0 4.0 db dc differential impedance r tx - diff - dc 72 120 ? ? the amount of voltage change allowed during receiver detection v tx - rcv - detect 0.6 v ac coupling capacitor c ac - coupling 75 200 nf maximum slew rate t cdr - slew - max 10 m s/s transmitter informative electrical parameters parameter symbol min max unit s deterministic min pulse t min - pulse - dj 0.96 ui tx min pulse t min - pulse - tj 0.90 ui transmitt er eye t tx - eye 0.625 ui tx deterministic jitter t tx - dj - dd 0.205 ui tx input capacitance for return loss c tx - parasitic 1.25 pf transmitter dc common mode impedance r tx - dc 18 30 ? transmitter short - circuit current limit i tx - short 60 ma transmitter dc common - mode voltage v tx - dc - cm 0 2.2 v tx ac common mode voltage v tx - cm - ac - pp - active 100 mvp - p absolute dc common mode voltage between u1 and u0 v tx - cm - dc - active - idle - delta 200 mv electrical idle differential peak - peak output voltage v tx - idle - diff - ac - pp 0 10 mv dc electrical idle differential output voltage v tx - idle - diff - dc 0 10 mv www.datasheet.co.kr datasheet pdf - http://www..net/ preliminary data sheet 17 ? pd 720 200 usb 3.0 superspeed interface C differential receiver (r x) specifications (refer to universal serial bus 3.0 specification revision 1.0 for more information) receiver normative electrical parameters parameter symbol min max unit s unit interval ui 199.94 200.06 ps receiver dc common mode impedance r rx - dc 18 30 ? ? dc differential impedance r rx - diff - dc 72 120 ? ? dc input cm input impedance for v>0 during reset of power down z rx - high - imp - dc - pos 25k ? lfps detect threshold v rx - lfps - de t - diff - p - p 100 300 mv receiver informative electrical parameters parameter symbol min max unit s differential rx peak - to - peak voltage v rx - diff - pp - post - eq 30 mv max rx inherent timing error t rx - tj 0.45 ui max rx in herent deterministic timing error t rx - dj - dd 0.285 ui rx input capacitance for return loss c rx - parasitic 1.1 pf rx ac common mode voltage v rx - cm - ac - p 150 mvpeak rx ac common mode voltage during the u1 to u0 transition v rx - cm - dc - active - idle - delta - p 200 mvpeak www.datasheet.co.kr datasheet pdf - http://www..net/ preliminary data sheet 18 ? pd 720 200 usb 2.0 interface (refer to universal serial bus specification revision 2.0 for more information) low - speed source electrical characteristics parameter symbol min max unit s driver characteristics: transition t ime: rise time fall time t lr t lf 75 75 300 300 ns ns rise and fall time matching t lrfm 80 125 % clock timings: low - speed data rate t ldraths 1.49925 1.50075 mb/s low - speed data timing: source jitter for differential transition to se0 transit ion t ldeop ? 40 100 ns source jitter total (including frequency tolerance): to next transition for paired transitions t ddj1 t ddj2 ? 25 ? 14 25 14 ns ns differential receiver jitter: to next transition for paired transitions t ujr1 t ujr2 ? 152 ? 200 152 200 ns ns source se0 interval of eop t leopt 1.25 1.50 ? s receiver se0 interval of eop t leopr 670 ns width of se0 interval during differential transition t lst 210 ns www.datasheet.co.kr datasheet pdf - http://www..net/ preliminary data sheet 19 ? pd 720 200 full - speed source electrical characteristics parameter symbol min max unit s driver characteristics: rise time t f r 4 20 ns fall time t f f 4 20 ns differential rise and fall time matching t f rfm 9 0 111.11 % clock timings: full - speed data rate t f draths 1 1.9940 12.0060 mb/s frame interval t frame 0.9995 1.0005 m s consecutive frame interval jitter t rfi 42 n s full - speed data timing: source jitter for differential transition to se0 transition t f deop ? 2 5 ns source jitter total (including frequency tolerance): to next transition for paired transitions t d j1 t d j2 ? 3.5 ? 4 3.5 4 ns ns receiver jitter: to next transition for paired tran sitions t jr1 t jr2 ? 1 8.5 ? 9 18.5 9 ns ns source se0 interval of eop t f eopt 160 175 n s receiver se0 interval of eop t f eopr 82 ns width of se0 interval during differential transition t f st 14 ns www.datasheet.co.kr datasheet pdf - http://www..net/ preliminary data sheet 20 ? pd 720 200 high - speed source electrical characteristics paramete r symbol min max unit s driver characteristics: rise time (10% - 90%) t hs r 500 p s fall time (10% - 90%) t hs f 500 p s driver waveform requirements figure 2 - 14 clock timings: high - speed data rate t hsd rat 497.760 480.240 mb/s microf rame interval t hsf rame 124.9375 125.0625 ? s consecutive microf rame interval difference t hsrfi 4 high - speed bit times high - speed data timing: data source jitter figure 2 - 14 receiver jitter tolerance figure 2 - 12 hub event timings parameter symbol min max unit s time to detect a downstream facing port connect event t dcnn 2.5 2000 ? s time to detect a disconnect event at a hub s downstream facing port t ddis 2 2.5 ? s duration of driving resume to a downstream port t drsmdn 20 m s time from detecting downstream resume to rebroadcast t ursm 1.0 m s inter - packet d elay for packets traveling in same direction t hsipd sd 88 b it times inter - packet d elay for packets traveling in opposite direction t hsipdo d 8 b it times inter - packet delay for root hub response for high - speed t hsrspipd1 192 b it times time for which a chirp j or chirp k must be continuously detected by hub during reset handshake t filt 2.5 ? s time after end of device chirp k by which hub must start driving first chirp k in the hub s chirp sequence t dchbit 100 ? s time for which each individual chirp j or chirp k in the chirp sequence is driven downstream by hub during reset t dchbit 40 60 ? s time before end of reset by which a hub must end its downstream chirp sequence t dchse0 100 500 ? s www.datasheet.co.kr datasheet pdf - http://www..net/ preliminary data sheet 21 ? pd 720 200 spi type serial rom interface spi type serial rom interface signals timing ( spi mode 0) parameter symbol min. max. unit s spis ck clock frequency 32 mhz clock pulses width low t scllow ns clock pulses width high t sclhigh 9 ns spicsb disable time t scsdis 25 ns spicsb setup time t scssu 25 ns spicsb hold time t scsh 10 ns spis i setup time to spisck rising edge t sdwsu 5 ns spis i hold time from spisck rising edge t sdwh 5 ns spis o validate time from spisck falling edge t sdrvalid 9 ns spis o hold time from spisck falling edge t sdrh 0 ns spis o disable time from spicsb disabled t sdrdis 100 ns www.datasheet.co.kr datasheet pdf - http://www..net/ preliminary data sheet 22 ? pd 720 200 figure 2 - 1 . power up and reset figure 2 - 2 . pci express single - ended measurement points for absolute cross point and swing figure 2 - 3 . pci express single - ended measurement points for absolute cross point and swing p e r s t b v d d 3 3 & v d d 1 0 p o n r s t b p e c l k p p e c l k n x t 1 / x t 2 p o w e r s t a b l e x t 1 / x t 2 s t a b l e t p o n r s t p e c l k p ( n ) s t a b l e t p e r s t - c l k t p v p e r l p e c l k n p e c l k p p e c l k n p e c l k p www.datasheet.co.kr datasheet pdf - http://www..net/ preliminary data sheet 23 ? pd 720 200 figure 2 - 4 . pci e xpress single - ended measurement points for delta cross point figure 2 - 5 . pci express single - ended measurement points for rise and fall time matching figure 2 - 6 . pci express differential measurement points for duty cycle and period figure 2 - 7 . pci express differential m easurement points for rise and fall time p e c l k p p e c l k n p e c l k n p e c l k p p e c l k p p e c l k n p e c l k p p e c l k n p e c l k p p e c l k n www.datasheet.co.kr datasheet pdf - http://www..net/ preliminary data sheet 24 ? pd 720 200 figure 2 - 8 . pci express differential measurement points for ring - back figure 2 - 9 . pci express power - up pe creqb timing figure 2 - 10 . pci express pe creqb clock control timing p e c l k p p e c l k n v d d 3 3 & v d d 1 0 p e c r q b p e r s t b p e c l k p p e c l k n t p e r s t b - c l k v d d 3 3 v d d 1 0 v d d 3 3 & v d d 1 0 p e c r q b p e c l k p p e c l k n h i g h www.datasheet.co.kr datasheet pdf - http://www..net/ preliminary data sheet 25 ? pd 720 200 figure 2 - 11 . differential input sensitivity range for low - /full - speed figure 2 - 12 . r eceiver sensitivity for transceiver at u2 dp/ u2 dm figure 2 - 13 . receiver measurement fixtures www.datasheet.co.kr datasheet pdf - http://www..net/ preliminary data sheet 26 ? pd 720 200 figure 2 - 14 . transmit waveform for transceiver at u2 dp/ u2 dm figure 2 - 15 . transmitter measurem ent fixtures figure 2 - 16 . d ifferential data jitter for low - / full - speed d i f f e r e n t i a l d a t a l i n e s t p e r i o d c r o s s o v e r p o i n t s c o n s e c u t i v e t r a n s i t i o n s n * t p e r i o d + t x d j 1 p a i r e d t r a n s i t i o n s n * t p e r i o d + t x d j 2 www.datasheet.co.kr datasheet pdf - http://www..net/ preliminary data sheet 27 ? pd 720 200 figure 2 - 17 . d ifferential - to - eop transition skew an d eop width for low - /f ull - speed figure 2 - 18 . r eceiver jitter tolerance for low - /f ull - speed figure 2 - 19 . spi type serial rom signal timing d i f f e r e n t i a l d a t a l i n e s t p e r i o d c r o s s o v e r p o i n t s d i f f . d a t a - t o - s e 0 s k e w n * t p e r i o d + t x d e o p c r o s s o v e r p o i n t s e x t e n d e d s o u r c e e o p w i d t h : r e c e i v e r e o p w i d t h : t f e o p t t l e o p t t f e o p r t l e o p r d i f f e r e n t i a l d a t a l i n e s t p e r i o d t x j r t x j r 1 t x j r 2 c o n s e c u t i v e t r a n s i t i o n s n * t p e r i o d + t x j r 1 p a i r e d t r a n s i t i o n s n * t p e r i o d + t x j r 2 s p i c s b s p i s c k s p i s i s p i s o www.datasheet.co.kr datasheet pdf - http://www..net/ preliminary data sheet 28 ? pd 720 200 3. package drawings ? ? pd720 20 0 f1 - dak - a www.datasheet.co.kr datasheet pdf - http://www..net/ preliminary data sheet 29 ? pd 720 200 4. recommended soldering conditions the ? pd720 20 0 should be soldered and mounted under the following recommended conditions. for soldering methods and conditions other than those recommended below, contact an nec electronics sales representative. for technical information, see the following website. semiconductor device mount manual (http://www.necel.com/pkg/en/mount/index.htm l) ? ? pd 720 20 0 f1 - dak - a: 176 - pin plastic fbga (1 0 1 0 ) soldering method soldering conditions symbol infrared reflow peak packages surface temperature: 260c, reflow time: 60 seconds or less (220c or higher), maximum allowable number of reflow processes: 3 , exposure limit note : 7 days (10 hours pre - backing is required at 125c afterwards), flux: rosin flux with low chlorine (0.2 wt% or below) recommended. preliminary data sheet 30 ? pd 720 200 [memo] www.datasheet.co.kr datasheet pdf - http://www..net/ preliminary data sheet 31 ? pd 720 200 www.datasheet.co.kr datasheet pdf - http://www..net/ all logo, trademarks or registered trademarks m entioned in this document are the intellectual property of their respective owners. www.datasheet.co.kr datasheet pdf - http://www..net/ |
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